/** @file
Iort table platform libary header file.

Copyright (C) 2023, Phytium Technology Co Ltd. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

**/

#ifndef IORT_TABLE_LIB_H_
#define IORT_TABLE_LIB_H_

#include <Protocol/ConfigurationManagerProtocol.h>
#include <Uefi/UefiBaseType.h>

#define PLAT_RC_COUNT                8    //one per socket
#define PLAT_SMMUV3_COUNT            32   //three per socket
#define PLAT_ITS_GROUP_COUNT         32   //four per socket
#define PLAT_ID_MAPPING_COUNT        64   //eight per socket
#define PLAT_ITS_IDENTIFIER_COUNT    32   //four per socket
#define PLAT_RC_IDMAPING_COUNT       8
#define PLAT_SMMU0_IDMAPING_COUNT    8
#define PLAT_CEU_COUNT               8

// PCI Bifurcation
#define PCI_BYPASS   0x0
#define X16          0x1
#define X8X8         0x2
#define X8X4X4       0x3
#define X4X4X4X4     0x4
#define X1X1X1X1     0x4

#define X8_C2C       0x4
#define C2C_X8       0x5
#define C2C_C2C      0x6

//Node Token
#define ROOT_COMPLEX_NODE_TOKEN          0x1
#define ITS_NODE_0_TOKEN                 0x2
#define ITS_NODE_1_TOKEN                 0x3
#define ITS_NODE_2_TOKEN                 0x4
#define ITS_NODE_3_TOKEN                 0x5
#define SMMUV3_NODE_0_TOKEN              0x6
#define SMMUV3_NODE_1_TOKEN              0x7
#define SMMUV3_NODE_2_TOKEN              0x8
#define CEU_SMMUV3_NODE_TOKEN            0x9
#define CEU_NODE_TOKEN                   0xa

#define ITS_ID_TOKEN                     0x0
#define ITS_0_ID_TOKEN                   0x0
#define ITS_1_ID_TOKEN                   0x1
#define ITS_2_ID_TOKEN                   0x2
#define ITS_3_ID_TOKEN                   0x3

#define ROOT_COMPLEX_ID_MAPPING_TOKEN    0x1
#define SMMUV3_NODE_0_ID_MAPPING_TOKEN   0x2
#define SMMUV3_NODE_1_ID_MAPPING_TOKEN   0x3
#define SMMUV3_NODE_2_ID_MAPPING_TOKEN   0x4
#define CEU_ID_MAPPING_TOKEN             0x5

#define ROOT_COMPLEX_ID_MAPPING_OFFSET   0x0
#define SMMUV3_NODE_0_ID_MAPPING_OFFSET  0x4
#define SMMUV3_NODE_1_ID_MAPPING_OFFSET  0x6
#define SMMUV3_NODE_2_ID_MAPPING_OFFSET  0x7


#define GIC_ITS_INDENTIFEIR_COUNT        0x4
#define ROOT_COMPLEX_COUNT               0x1
#define SMMU_NODE_COUNT                  0x3
#define ITS_GROUP_COUNT                  0x4

//Pcie Related
#define PCI_CONFIG_BASE                  0x40000000
#define PRIMARY_BUS_REG                  0x18

//Smmu Related
#define PCI0_SMMU_BASE                   0x3B200000
#define PCI1_SMMU_BASE                   0x3A200000
#define PCI2_SMMU_BASE                   0x3AA00000
#define CEU_SMMU_BASE                    0x3BC00000

#define SMMU_INTERRUPT_OFSSET            96
#define EVENT_INTERRUPT_BASE             94
#define EVENT_INTERRUPT_OFFSET           8
#define PRI_INTERRUPT_BASE               122
#define PRI_INTERRUPT_OFFSET             2
#define GERR_INTERRUPT_BASE              121
#define GERR_INTERRUPT_OFFSET            2
#define SYNC_INTERRUPT_BASE              93
#define SYNC_INTERRUPT_OFFSET            8

#define CEU_EVENT_INTERRUPT_BASE         82
#define CEU_PRI_INTERRUPT_BASE           120
#define CEU_GERR_INTERRUPT_BASE          119
#define CEU_SYNC_INTERRUPT_BASE          81


typedef struct {
  CM_ARM_ROOT_COMPLEX_NODE              RootComplexInfo[PLAT_RC_COUNT];
  CM_ARM_ITS_GROUP_NODE                 ItsGroupInfo[PLAT_ITS_GROUP_COUNT];
  CM_ARM_ITS_IDENTIFIER                 ItsIdentifierInfo[PLAT_ITS_IDENTIFIER_COUNT];
  CM_ARM_SMMUV3_NODE                    SmmuV3Info[PLAT_SMMUV3_COUNT];
  CM_ARM_ID_MAPPING                     IdMappingInfo[PLAT_ID_MAPPING_COUNT];
  UINT8                                 RootComplexIdMappingCount[PLAT_RC_IDMAPING_COUNT];
  UINT8                                 Smmu0IdMappingCount[PLAT_SMMU0_IDMAPING_COUNT];
  CM_ARM_NAMED_COMPONENT_NODE           CeuNode[PLAT_CEU_COUNT];
  CM_ARM_ID_MAPPING                     CeuIdMappings[PLAT_CEU_COUNT];
} PLATFORM_INFO;


#endif


